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M368L1713CTL
184pin Unbuffered DDR SDRAM MODULE
128MB DDR SDRAM MODULE
(16Mx64 based on 16Mx8 DDR SDRAM)
Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
Revision 0.3 May. 2002
Rev. 0.3 May. 2002
M368L1713CTL
Revision History
Revision 0.0 (Oct. 2001)
1. First release
184pin Unbuffered DDR SDRAM MODULE
Revision 0.1 (Nov. 2001)
1. Added DDR333 function 2. Updated DDR333 test specification 3. Deleted typical current in IDD spec. table 4. Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification 5. Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification 6. Changed unit of tMRD from tCK to ns at DDR333 7. Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266 8. Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266 9. Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266 10. Rename tREF(Refresh interval time) to tREFI at DDR200/266 11. Rename tCDLR(Last write data to Read command) to tWTR
Revision 0.2 (Jan. 2002)
1. Added tRAP(Active to Read with auto precharge command)
Revision 0.3 (May. 2002)
1. Change pin location of A13 from pin 103 to pin 167
Rev. 0.3 May. 2002
M368L1713CTL
184pin Unbuffered DDR SDRAM MODULE
M368L1713CTL DDR SDRAM 184pin DIMM
16Mx64 DDR SDRAM 184pin DIMM based on 16Mx8 GENERAL DESCRIPTION FEATURE
The Samsung M368L1713CTL is 16M bit x 64 Double Data Rate SDRAM high density memory modules. The Samsung M368L1713CTL consists of eight CMOS 16M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOPII(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M368L1713CTL is Dual In-line Memory Modules and intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * Performance range Part No. Max Freq. Interface SSTL_2 M368L1713CTL-C(L)B3 166MHz(6ns@CL=2.5) M368L1713CTL-C(L)A2 133MHz(7.5ns@CL=2) M368L1713CTL-C(L)B0 133MHz(7.5ns@CL=2.5) * Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height 1250 mil , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin Front Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 *CB0 *CB1 VDD *DQS8 A0 *CB2 VSS *CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 *CKE1 VDDQ *BA2 DQ20 *A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK0 /CK0 VSS *DM8 A10 *CB6 VDDQ *CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 Pin Back 154 /RAS 155 DQ45 156 VDDQ 157 /CS0 158 */CS1 159 DM5 160 VSS 161 DQ46 162 DQ47 163 */CS3 164 VDDQ 165 DQ52 166 DQ53 167 *A13 168 VDD 169 DM6 170 DQ54 171 DQ55 172 VDDQ 173 NC 174 DQ60 175 DQ61 176 VSS 177 DM7 178 DQ62 179 DQ63 180 VDDQ 181 SA0 182 SA1 183 SA2 184 VDDSPD
PIN DESCRIPTION
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS7 CKE0 /CS0 RAS CAS WE DM0 ~ DM7 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock enable input Chip select input Row address strobe Column address strobe Write enable Data - in mask Power supply (2.5V) Power Supply for DQ S(2.5V) Ground Power supply for reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VDD identification flag
CK0,CK0 ~ CK2,CK2 Clock input
NC No connection * These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.3 May. 2002
M368L1713CTL
Functional Block Diagram
184pin Unbuffered DDR SDRAM MODULE
DQS0 DM0
CS0
DQS4 DM4
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
D0
D4
DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS5 DM5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D1
D5
DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D2
D6 * Clock Wiring Clock Input C K 0 /CK0 C K 1 /CK1 C K 2 /CK2
C S DQS
SDRAMs 2 SDRAMs 3 SDRAMs 3 SDRAMs
DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS7 DM7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D3
D7 *Clock Net Wiring Dram1
Cap R=120 D r am3 *(Cap) Cap Dram5
Serial PD BA0 - BA1 A0 - A 13 RAS CAS CKE0 WE V DDSPD V DD/V DDQ BA0-BA1: SDRAMs D0 - D7 A0-A13: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE : SDRAMs D0 - D7 SPD D0 - D7 D0 - D7 VREF V SS D0 - D7 D0 - D7 SA0 SA1 SA2 SCL WP A0 A1 A2 SDA Card Edge
Cap *If two DRAMs are loaded, Cap will replace DRAM3
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.3 May. 2002
M368L1713CTL
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VD D supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation Short circuit current
184pin Unbuffered DDR SDRAM MODULE
Symbol VIN, VOUT VDD VDDQ TSTG PD IOS
Value -0.5 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 12 50
Unit V V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C)
Parameter
Supply voltage(for device with a nominal V DD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input crossing point voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = V TT - 0.84V Output High Current(Half strengh driver) ;VOUT = V TT + 0.45V Output High Current(Half strengh driver) ;VOUT = V TT - 0.45V
Symbol
VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL
Min
2.3 2.3 VDDQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ +0.3 VREF-0.15 VDDQ +0.3 VDDQ +0.6 1.35 2 5
Unit
Note
V V V V V V V V uA uA mA mA mA mA 3 5 1 2 4 4
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on V REF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF and internal DRAM noise coupled TO VREF, both of which may result in V REF noise. VREF should be de-coupled with an inductance of 3nH. 2.VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of V R E F 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.3 May. 2002
M368L1713CTL
DDR SDRAM IDD spec table
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 880 1120 32 256 160 320 440 1280 1280 1680 16 8 3200
184pin Unbuffered DDR SDRAM MODULE
(Vdd = 2.7V, T= 10' C) A2(DDR266@CL=2) 760 1000 32 200 120 240 440 1240 1240 1600 16 8 2800 B0(DDR266@CL=2.5) 760 1000 32 200 120 240 440 1240 1240 1600 16 8 2800 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC OPERATING CONDITIONS
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V Note 3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition
(VDD=2.5V, VDDQ=2.5V, T A= 0 to 70 C)
Value 0.5 * VDDQ 1.5 VREF+0.31/VREF-0.31 VREF Vtt See Load Circuit Unit V V V V V Note
Rev. 0.3 May. 2002
M368L1713CTL
184pin Unbuffered DDR SDRAM MODULE
Vtt=0.5*V DDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE
Parameter
(VDD=2.5V, V DDQ=2.5V, TA= 25C, f=1MHz) Symbol C IN1 C IN2 C IN3 C IN4 COUT C IN5 Min 49 42 42 22 6 6 Max 57 50 50 25 8 8 Unit pF pF pF pF pF pF
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE ) Input capacitance(CKE 0) Input capacitance( CS0) Input capacitance( CLK 0, CLK1,CLK2 ) Data & DQS input/output capacitance(DQ0~DQ 63) Input capacitance(DM0~DM8)
Rev. 0.3 May. 2002
M368L1713CTL
184pin Unbuffered DDR SDRAM MODULE
tested on the Component)
-TCB0 (DDR266B) Min
65 75 120K 45 20 20 15 15 1 1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 1.1 0.9 0.9 0.9 1.0 1.0 +0.75 +0.75 -0.75 -0.75 0.5 0.5 4.5 1.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
AC Timming Parameters & Specifications (These AC charicteristics were
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/ CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/ CK Data-out low impedence time from CK/ CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR
-TCB3 (DDR333) Min
60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 4.5 1.5 +0.7 +0.7 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K
-TCA2 (DDR266A) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67
Unit
ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns V/ns V/ns V/ns
Note
Max
Max
Max
5 5
5
2
6 6 6 6
6 7 10
Rev. 0.3 May. 2002
M368L1713CTL
Parameter
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time
184pin Unbuffered DDR SDRAM MODULE
Symbol
tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP 0.4 20 (tWR/tCK) + (tRP/tCK)
-TCB3 (DDR266A) Min
12 0.45 0.45 2.2 1.75 6 75 200 15.6 tHP -tQHS tCLmin or tCHmin 0.55 0.6
-TCA2 (DDR266A) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 15.6 tHP -tQHS tCLmin or tCHmin 0.75 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6
-TCB0 (DDR266B) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 15.6 tHP -tQHS tCLmin or tCHmin 0.75 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6
Unit
ns ns ns ns ns ns ns tCK us ns ns ns tCK
Note
Max
Max
Max
7,8,9 7,8,9
4
1 5
3
tDAL
tCK
11
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with t RCD satisfied after this command. 5. For registered DIMMs, t CL and tCH are 45% of the period including both the half period jitter (t JIT(HP)) of the PLL and the half period jitter due to crosstalk (t JIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150
This derating table is used to increase t DS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 0.3 May. 2002
M368L1713CTL
8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tDS (ps) +50
184pin Unbuffered DDR SDRAM MODULE
tDH (ps) +50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS /tD H in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0 V/ns. CK slew rate (Single ended) 1.0V/ns 0.75V/ns 0.5V/ns tIH/tIS (ps) 0 +50 +100 tDSS/tDSH (ps) 0 +50 +100 tAC/tDQSCK (ps) 0 +50 +100 tLZ(min) (ps) 0 -50 -100 tHZ(max) (ps) 0 +50 +100
Rev. 0.3 May. 2002
M368L1713CTL
Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
184pin Unbuffered DDR SDRAM MODULE
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
CKEn-1 CKEn CS RAS CAS WE BA0,1 A10 /AP A11 A9 ~ A 0 Note
H H H
X X H L H X X
L L L L H L L
L L L H X L H
L L L H X H L
L L H H X H H V V
OP CODE OP CODE X
1, 2 1, 2 3 3 3 3
L H H
X Row Address L H L
Column Address (A0~ A9) Column Address (A0~ A9)
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4 4 4, 6 7
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
V
H X
V X
L H
X
5
Active Power Down
H L H
L H L
X
X
L H H
H
X X H X H X
8 9 9
X
H L
X H
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A 10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.3 May. 2002
M368L1713CTL
PACKAGE DIMENSIONS
184pin Unbuffered DDR SDRAM MODULE
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.077 (128.950) 1.25 0.006 (31.75 0.15) (2X) 0.157 (4.00)
0.118 (3.00)
0.100 Min (2.30 Min)
A
B
2.500
0.10 M C BA
2.55
1.95
(64.77)
(49.53)
(2.50 )
0.26 (6.62)
0.100
0.250 (6.350)
0.157 (4.00)
0.039 0.002 (1.000 0. 050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15) 0.050 (1.270) 0.1575 (4.00) 0.10 M C A M B
0.118 (3.00)
0.1496 (3.80)
2.175
0.071 (1.80)
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified. The used device is 16Mx8 DDR SDRAM, TSOP. SDRAM Part NO : K4H280838C.
Rev. 0.3 May. 2002
(10.00)
0.393
0.07 Max (1.20 Max)
0.050 0.0039 (1.270 0.10)
0.7 (17.80)

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